LT3596
APPLICATIONS INFORMATION
losses. Some applications require very low duty cycles to
drive a small number of LEDs from a high supply. Low
switching frequency allows a greater range of operational
duty cycle and so a lower number of LEDs can be driven.
In each case, the switching frequency can be tailored to
provide the optimum solution. When programming the
switching frequency, the total power losses within the IC
should be considered.
Table 8. R T Resistor Selection
R T VALUE (kΩ) SWITCHING FREQUENCY (MHz)
33.2 1.0
80.6 0.5
220 0.2
The SYNC pin must be grounded if the clock synchroniza-
tion feature is not used. When the SYNC pin is grounded,
the internal oscillator controls the switching frequency of
the converter.
Operating Frequency Trade-Offs
Selection of the operating frequency is a trade-off between
efficiency, component size, input voltage and maximum
output voltage. The advantage of high frequency operation
is smaller component size and value. The disadvantages
are lower efficiency and lower maximum output voltage
for a fixed input voltage. The highest acceptable switch-
ing frequency (f SW(MAX) ) for a given application can be
calculated as follows:
f SW ( MAX ) =
1.2
1.0
0.8
0.6
0.4
0.2
0
0
55
110
165
220
V D + V OUT
t ON ( MIN ) ( V D + V IN – V SW )
where V IN is the typical input voltage, V OUT is the output
voltage, V D is the catch diode drop (~0.5V) and V SW is the
internal switch drop (~0.4V at max load). This equation
shows that slower switching is necessary to accommodate
high V IN /V OUT ratios. The input voltage range depends on
the switching frequency due to the finite minimum switch
on and off times. The switch minimum on and off times
are 150ns.
R T (k )
3596 F10
Adaptive Loop Control
R1
Figure 10. Programming Switching Frequency
Switching Frequency Synchronization
The nominal operating frequency of the LT3596 is pro-
grammed using a resistor from the RT pin to ground. The
frequency range is 200kHz to 1MHz. In addition, the internal
oscillator can be synchronized to an external clock applied
to the SYNC pin. The synchronizing clock signal input to
the LT3596 must have a frequency between 240kHz and
1MHz, a duty cycle between 20% and 80%, a low state
below 0.4V and a high state above 1.6V. Synchronization
signals outside of these parameters cause erratic switching
behavior. For proper operation, an R T resistor is chosen
to program a switching frequency 20% slower than the
SYNC pulse frequency. Synchronization occurs at a fixed
delay after the rising edge of SYNC.
The LT3596 uses an adaptive control mechanism to set
the buck output voltage. This control scheme ensures
maximum efficiency while not compromising minimum
PWM pulse widths. When any PWM n is low, the output
of the buck rises to a maximum value set by an external
resistor divider to the FB pin. When all PWM n pins go
high, the output voltage is adaptively reduced until the
voltage across the LED current sink is about 1V. Figure
11 shows how the maximum output voltage is set by an
external resistor divider.
V OUT V OUT
R2 LT3596
FB
3596 F11
Figure 11. Programming Maximum V OUT
3596fa
  
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